NDLI: Integrated CUDA-to-FPGA Synthesis with Network-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Gurumani, S.T. Tolar, J. Yao Chen Yun Liang Rupnow, K. Deming Chen
Copyright Year	2014
Description	Author affiliation: Sch. of EECS, Peking Univ., Beijing, China (Yun Liang) \|\| Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA (Tolar, J.; Yao Chen) \|\| Nanyang Technol. Univ., Singapore, Singapore (Rupnow, K.) \|\| Adv. Digital Sci. Center, Singapore, Singapore (Gurumani, S.T.; Deming Chen)
Abstract	Data parallel languages such as CUDA and Open CL efficiently describe many parallel threads of computation, and HLS tools can effectively translate these descriptions into independent optimized cores. As the number of instantiated cores grows, average external memory access latency can be a significant factor in system performance. However, although each core produces outputs independently, the cores often heavily share input data. Exploiting on-chip data sharing both reduces external bandwidth demand and improves the average memory access latency, allowing the system to improve performance at the same number of cores. In this paper, we develop a network-on-chip coupled with computation cores synthesized from CUDA for FPGAs that enables on-chip data sharing. We demonstrate reduced external bandwidth demand by up to 60% (average 56%) and total application latency in cycles by up to 43% (average 27%).
Starting Page	21
Ending Page	24
File Size	436440
Page Count	4
File Format	PDF
e-ISBN	9781479951116
DOI	10.1109/FCCM.2014.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics processing units Bandwidth Field programmable gate arrays Kernel Ports (Computers) Network-on-chip Memory bandwidth High-level Synthesis CUDA NoC Directory protocol
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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