NDLI: Towards evolving industry-feasible intrinsic variability tolerant CMOS designs

Content Provider	IEEE Xplore Digital Library
Author	Walker, J.A. Hilder, J.A. Tyrrell, A.M.
Copyright Year	2009
Description	Author affiliation: Intelligent Systems Group, Department of Electronics, University of York, Heslington, YO10 5DD, UK (Walker, J.A.; Hilder, J.A.; Tyrrell, A.M.)
Abstract	As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. This paper introduces a design tool capable of evolving CMOS topologies using a modified form of Cartesian Genetic Programming and a multi-objective strategy. The effect of intrinsic variability within the design is then analysed using statistically enhanced SPICE models based on 3D-atomistic simulations. The goal is to produce industry-feasible topology designs which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. The results show evolved XOR and XNOR CMOS topologies and compare the impact of threshold voltage variation on the evolved designs with those from a standard cell library.
Starting Page	1591
Ending Page	1598
File Size	1509134
Page Count	8
File Format	PDF
ISBN	9781424429585
DOI	10.1109/CEC.2009.4983132
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-18
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Libraries MOSFETs Semiconductor device modeling CMOS technology Integrated circuit technology Circuit topology Fabrication Genetic programming SPICE
Content Type	Text
Resource Type	Article

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