NDLI: Design of high speed low power viterbi decoder for TCM system

Content Provider	IEEE Xplore Digital Library
Author	Nargis, J. Vaithiyanathan, D. Seshasayanan, R.
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Anna Univ., Chennai, India (Nargis, J.; Vaithiyanathan, D.; Seshasayanan, R.)
Abstract	Viterbi decoder is the most power hungry module in the Trelli coded modulation system. In VLSI implementation, reduced chip area, low power consumption, improved speed are the main concerns to be obtained. In this brief, high speed low power Viterbi algorithm architecture is proposed to decode the high rate convolution codes. Constraint length of high rate convolution code should be high to maintain low error probability. But computational complexity of the Viterbi algorithm for high rate convolution code increases exponentially with the constraint length. This computational problem can be solved by trimming the least likely paths at each trelli stage in the T-algorithm; as a result significant power reduction can also be achieved. Furthermore, the pre-computation technique is used to speed up the process of searching for the optimal path metric from the ACSU loop. Architecture of the Add-Compare-Select loop is modified using the pre-computation architecture. This shortens the long critical path introduced by the conventional T-algorithm. Register exchange algorithm is used for the survivor memory unit design, since it is faster and requires lesser memory. Conceptually, Register exchange algorithm has a pre-defined end state. Since the optimized T-algorithm is used, pre-defining the end state is not possible. This issue is focused and appropriate solution is provided in this paper. From the simulation results it is observed that the proposed Viterbi decoder architecture can reduce significant amount of computations, power consumption with negligible performance reduction.
Sponsorship	IEEE Madras Sect.
Starting Page	185
Ending Page	190
File Size	190581
Page Count	6
File Format	PDF
ISBN	9781467357869
e-ISBN	9781467357883
DOI	10.1109/ICICES.2013.6508239
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Measurement Convolutional codes VLSI Register exchange Viterbi decoder Decoding Registers Viterbi algorithm Convolution Pre-computation Computer architecture Convolution code State reduction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

Design of T-Algorithm Based High-Speed Low-Power Viterbi Decoder for TCM Decoders

High speed low power Soft-Output Viterbi decoder

Design of Trellis code modulation decoder using Hybrid Register Exchange Method

Low complexity FPGA implementation of Register Exchange Based Viterbi decoder

Algorithm of Low Complexity Viterbi Decoder in Convolutional Codes

Low-power register-exchange Viterbi decoder for high-speed wireless communications

High performance Viterbi decoder using modified register exchange methods

Low-power adaptive viterbi decoder for tcm using t-algorithm.

Design of high speed low power viterbi decoder for TCM system

Similar Documents

High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

Design of T-Algorithm Based High-Speed Low-Power Viterbi Decoder for TCM Decoders

High speed low power Soft-Output Viterbi decoder

Design of Trellis code modulation decoder using Hybrid Register Exchange Method

Low complexity FPGA implementation of Register Exchange Based Viterbi decoder

Algorithm of Low Complexity Viterbi Decoder in Convolutional Codes

Low-power register-exchange Viterbi decoder for high-speed wireless communications

High performance Viterbi decoder using modified register exchange methods

Low-power adaptive viterbi decoder for tcm using t-algorithm.

Design of high speed low power viterbi decoder for TCM system