NDLI: TLP Characterization and Leakage-Biasing-Voltage (VLB) Correlations in MOSFET Measurements

Content Provider	IEEE Xplore Digital Library
Author	Shen-Li Chen Min-Hua Lee
Copyright Year	2014
Description	Author affiliation: Dept. of of Electron. Eng., Nat. United Univ., Miaoli, Taiwan (Shen-Li Chen; Min-Hua Lee)
Abstract	An investigation of leakage-biasing-voltage $(V_{LB})$ influence on the final measurement data of TLP testing is proposed in this work. In order to identify the impact on electrostatic discharge (ESD) immunity evaluation, three kinds of MOSFET DUTs are used, which are the LVnMOS (5-V/0.6-um), HVnMOS and HVpMOS (12-V/0.6-um) technologies devices, respectively. After a series of systematic TLP measurement, it can be found that the above mentioned variable $(V_{LB})$ has a very serious repercussion on $I_{t2}$ values of LVnMOS and HVnMOS, but the influence on HVpMOS DUT is very minor. In terms of device measured $I_{t2}$ data, the error of experimental results here caused by a maximum leakage-biasing-voltage $(V_{LB})$ is up to 56% in LVnMOS DUTs, 81% in HVnMOS DUTs, and only 5% in HVpMOS DUTs, respectively. Therefore, it will result in many TLP test results of DUTs as compared to their HBM testing data with a considerable deviation. Then, in order to let the real TLP measured values have a good correlation with HBM's robustness on the same DUT, this setting parameter $(V_{LB})$ should be taken into account during the TLP measurement. It is shown that lack of correlation is caused by misinterpretations in the test results, due to the fact that soft and hard failure in a DUT. That is to measure a true $I_{t2}$ value of DUTs, a leakage-biasing-voltage $(V_{LB})$ state in the TLP testing should not be too high.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	199
Ending Page	202
File Size	374382
Page Count	4
File Format	PDF
ISBN	9781479952779
DOI	10.1109/IS3C.2014.62
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage measurement Correlation Transmission-line-pulse (TLP) Electrostatic discharges Human-body model (HBM) Leakage currents Leakage-biasing-voltage (VLB) Secondary breakdown current (It2) Current measurement Robustness Holding voltage (Vh) Testing Trigger voltage (Vt1)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs

Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications

Lower trigger voltage design for ESD protection device applied in PMIC application

ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

Drain-side discrete-distributed layout influences on reliability issues in the 0.25 μm 60-V power pLDMOS

Robust design of HV pLDMOS-ESCR structures in a 60-V BCD process

Notice of RetractionMeasurement of ESD protection structure irradiation degradation using TLP method

On the Electrostatic Discharge Robustness of Graphene

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

TLP Characterization and Leakage-Biasing-Voltage (VLB) Correlations in MOSFET Measurements

Similar Documents

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs

Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications

Lower trigger voltage design for ESD protection device applied in PMIC application

ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

Drain-side discrete-distributed layout influences on reliability issues in the 0.25 μm 60-V power pLDMOS

Robust design of HV pLDMOS-ESCR structures in a 60-V BCD process

Notice of RetractionMeasurement of ESD protection structure irradiation degradation using TLP method

On the Electrostatic Discharge Robustness of Graphene

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

TLP Characterization and Leakage-Biasing-Voltage (VLB) Correlations in MOSFET Measurements