NDLI: Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique

Content Provider	IEEE Xplore Digital Library
Author	Mishra, S. Akashe, S.
Copyright Year	2013
Description	Author affiliation: Dept. ITM, Univ. Gwalior, Gwalior, India (Akashe, S.) \|\| VLSI Design, ITM Univ., Gwalior, India (Mishra, S.)
Abstract	In this paper we introduced low leakage 10T one-bit full adders cells are proposed for mobile applications. The analysis has been performed on various process and circuits techniques, the analysis with leakage power. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and area to minimize leakage current. We have performed simulations using Cadence Virtuoso 45nm standard CMOS technology at room temperature with supply voltage of 0.7V. Simulations have been also compared for multiple VDD. Thus design guide-lines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare 1-bit adders implemented as a chain of one-bit full adders. The CMOS leakage current at the process level can be decreased by some implement on deep sub micron method. The circuit level technique is reduced power consumption at very high level. In this paper we simulate the 10T Adder using many techniques both circuit level, process level.
Starting Page	158
Ending Page	162
File Size	346412
Page Count	5
File Format	PDF
ISBN	9781467359658
ISSN	23270659
e-ISBN	9780769549415
DOI	10.1109/ACCT.2013.39
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS Doping MOSFET Transistor Leakage and Threshold Voltage Inverters Threshold voltage CMOS integrated circuits Leakage currents Transistors Adder Adders
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design high performance and low power 10T full adder cell using double gate MOSFET at 45nm technology

Design low power 10T full adder using process and circuit techniques

An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits

A low power 16 bit BCD adder using different power reduction techniqes

Optimization of Static Power, Leakage Power and Delay of Full Adder Circuit Using Dual Threshold MOSFET Based Design and T-Spice Simulation

Standby and active leakage current control mechanism of half adder cell

Transistor gating: Reduction of leakage current and power in full subtractor circuit

Comparative analysis of carry select adder using 8T and 10T full adder cells

Effect of process, voltage and temperature (PVT) variations In LECTOR-B (leakage reduction technique) at 70 nm technology node

Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique

Similar Documents

Design high performance and low power 10T full adder cell using double gate MOSFET at 45nm technology

Design low power 10T full adder using process and circuit techniques

An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits

A low power 16 bit BCD adder using different power reduction techniqes

Optimization of Static Power, Leakage Power and Delay of Full Adder Circuit Using Dual Threshold MOSFET Based Design and T-Spice Simulation

Standby and active leakage current control mechanism of half adder cell

Transistor gating: Reduction of leakage current and power in full subtractor circuit

Comparative analysis of carry select adder using 8T and 10T full adder cells

Effect of process, voltage and temperature (PVT) variations In LECTOR-B (leakage reduction technique) at 70 nm technology node

Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique