NDLI: Security-aware VLSI design for speaker identification based on efficient SMO architecture

Content Provider	IEEE Xplore Digital Library
Author	Jhing-Fa Wang Jr-Shiang Peng Po-Chuan Lin Bo-Wei Chen Nai-Sheng Shihi
Copyright Year	2011
Description	Author affiliation: Department of Electronics Engineering and Computer Science, Tung Fang Design University, Kaohsiung Country, Taiwan (Po-Chuan Lin) \|\| Department of Electrical Engineering, National Cheng Kung University, Tainan City, Taiwan (Jhing-Fa Wang; Jr-Shiang Peng; Bo-Wei Chen; Nai-Sheng Shihi)
Abstract	Speaker identification is a popular investigation that is greatly applied in many applications such as human-machine interfaced, security systems, etc. In real life, low cost and fast response are both necessary features for speaker identification in stand-alone embedded device. However, most of the responding time occupies in training phase, and the cost of general solution by employing digital signal processors is too high. In this work, security-aware VLSI design with the efficient Sequential Minimal Optimization (SMO) architecture is proposed for solving the problems in text-independent speaker identification. Our contributions are attributed to the optimal VLSI design form algorithm to architecture level. At algorithm level, the proposed Improved SMO (ISMO) algorithm is adopted for efficient data selection and it can reduce 30% computation. At architecture level, a distributed and reconfigurable computing architecture which combines parallel and pipeline designing styles is implemented, and it provides the high flexible and high performance benefits. Finally, the experimental results show that the proposed design can save 50% of memory usage, and the hardware resources can be reduced by 31% than our previous work. Furthermore, the responding time can decrease 85%.
Starting Page	362
Ending Page	365
File Size	759249
Page Count	4
File Format	PDF
ISBN	9781457708879
e-ISBN	9781457708886
DOI	10.1109/ICAwST.2011.6163100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLSI Computer architecture Very large scale integration Security-Aware Reconfigurable Computing Speaker Identification SMO
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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