NDLI: High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology

Content Provider	IEEE Xplore Digital Library
Author	Das, A. Mandal, S.K. Das, J.K.
Copyright Year	2015
Description	Author affiliation: Sch. Of Electron., KIIT Univ., Bhubaneswar, India (Das, A.; Mandal, S.K.; Das, J.K.)
Abstract	In the research area of VLSI system design the Adders have always been the fundamental requirements for high performance processors and multi-core devices. On the basis of area, delay and power consumption, different adder circuits are proposed but the trade off between these performance metrics forces to choose the efficient circuits for data path design. This Proposed Structure is based on the Multi-Threshold CMOS (MTCMOS) based D-Latch instead of using Binary to Excess-1(BEC) or (Ripple Carry Adder)RCA for $C_{in}=0.$ This work has been evaluated for 8-bit Square Root Carry Select Adder (SQRT CSLA) in terms of delay and power in Cadence Virtuoso environment 45nm CMOS process technology in room temperature with supply voltage 1volt. D-Latch based circuit has reduced Delay of 42.21% where as proposed MTCMOS based D-latch based circuits has 50.27% delay minimization as compared to BEC converter based SQRT CSLA. There is 13.94% delay and the 5.70% power have been reduced in MTCMOS D-Latch circuits when compared with the D-Latch based SQRT CSLA.
Starting Page	1
Ending Page	4
File Size	220589
Page Count	4
File Format	PDF
ISBN	9781479976768
e-ISBN	9781479976782
DOI	10.1109/EESCO.2015.7253977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-24
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing BEC Latches SQRT CSLA Logic gates MTCMOS D-Latch Delays Transistors Adders Switching circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient carry select adder using 0.12µm technology for low power applications

A comparative study on low-power and high speed Carry Select Adder

Modified wallace tree multiplier using efficient square root carry select adder

A novel high speed MCML square root carry select adder for mixed-signal applications

Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)

Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)

Leakage power reduction in MTCMOS based high speed adders

High speed carry select adder for alu blocks.

Design of high efficiency carry select adder using sqrt technique.

High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology

Similar Documents

Efficient carry select adder using 0.12µm technology for low power applications

A comparative study on low-power and high speed Carry Select Adder

Modified wallace tree multiplier using efficient square root carry select adder

A novel high speed MCML square root carry select adder for mixed-signal applications

Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)

Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)

Leakage power reduction in MTCMOS based high speed adders

High speed carry select adder for alu blocks.

Design of high efficiency carry select adder using sqrt technique.

High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology