NDLI: Hybrid type test pattern generator for memory testing

Content Provider	IEEE Xplore Digital Library
Author	Ravi Shankar Reddy, C. Sumalatha, V.
Copyright Year	2015
Description	Author affiliation: ECE Dept., Jawaharlal Nehru Technol. Univ., Anantapur, India (Ravi Shankar Reddy, C.) \|\| Coll. of Eng., ECE Dept., JNTUA, Anantapur, India (Sumalatha, V.)
Abstract	This paper describes Hybrid type Built in Self-Test Pattern Generator which is employed for identifying all easy to detect as well as hard to detect faults that will occur in memories. The testing of memory by the proposed Hybrid BIST TPG is carried under two phases. In the first phase of testing MLTRTPG is employed to identify easy to detect faults. And other phase of testing is carried out by Adder based 3-Weighted Random Test Pattern Generator (A3-WRTPG) to detect all RPRF's that are dropped by MLTRTPG. The proposed Hybrid type of BIST-TPG can effectively reduce peak power and average power consumption at test time. The proposed BISTTPG also achieves very high fault coverage. Experiments conducted on memory architectures like RAM and ROM convey fact that the proposed Hybrid Type of Built in self- test TPG is successful in achieving power saving, while achieving 100% fault coverage.
Starting Page	1
Ending Page	6
File Size	493171
Page Count	6
File Format	PDF
ISBN	9781479976768
e-ISBN	9781479976782
DOI	10.1109/EESCO.2015.7253652
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-24
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand A3WRTPG BIST Built-in self-test Logic gates MLTRTPG TPG Circuit faults Test pattern generators Adders
Content Type	Text
Resource Type	Article

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