NDLI: Performance evaluation of low voltage Schmitt triggers using variable Threshold techniques

Content Provider	IEEE Xplore Digital Library
Author	Joseph, J.S. Shukla, R. Niranjan, V.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Indira Gandhi Delhi Tech. Univ. for Women, Delhi, India (Joseph, J.S.; Shukla, R.; Niranjan, V.)
Abstract	In this paper, a low voltage Schmitt trigger has been designed using various low voltage MOS transistor implementation techniques namely-Dynamic Threshold MOS (DTMOS), Multiple threshold MOS (MTMOS), Variable threshold MOS (VTMOS) and Floating gate MOS (FGMOS). The conventional and proposed circuits are designed in 180nm CMOS technology from TSMC and simulated at 0.5 Volts. The comparative study of the performance of proposed Schmitt triggers in terms of width of the hysteresis curve, delay introduced and power dissipation for same inputs and supply voltages has been done and based on the results obtained, application for each Schmitt trigger has been suggested.
Starting Page	1
Ending Page	5
File Size	426680
Page Count	5
File Format	PDF
e-ISBN	9781467372312
DOI	10.1109/ICRITO.2015.7359347
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VTMOS MOSFET Schmitt Trigger DTMOS Logic gates Threshold voltage CMOS integrated circuits Power dissipation FGMOS Hysteresis MTMOS
Content Type	Text
Resource Type	Article

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Performance evaluation of low voltage Schmitt triggers using variable Threshold techniques