NDLI: Design of Fault Tolerant Arithmetic & Logical Unit Using Reversible Logic

Content Provider	IEEE Xplore Digital Library
Author	Kaur, T. Singh, N.
Copyright Year	2013
Description	Author affiliation: Electron. & Commun. Eng., Guru Nanak Dev Eng. Coll., Ludhiana, India (Kaur, T.; Singh, N.)
Abstract	In VLSI designs today, the device dimensions are shrinking and the circuit complexity is also growing exponentially. This device scaling leads to power dissipation, demanding for better power optimizations methods. Also when output is generated in conventional logic circuits the input vector gets lost. Losing information in a circuit causes losing power. The gate/circuit that does not loose information is called reversible gate. Energy dissipation would not occur, if a computation is done in a reversible way. In this paper, the basic concepts of reversible circuits are briefly discussed. Furthermore, an efficient & low cost fault tolerant reversible Arithmetic and logical unit (ALU) is designed and implemented. The results are then compared with the existing design. The large garbage outputs in the proposed design are compensated by the number of operations that it can perform. The Proposed design can perform almost all arithmetic and logical operations on the other hand existing design performs only four operations.
Starting Page	331
Ending Page	334
File Size	403140
Page Count	4
File Format	PDF
ISBN	9780769550138
DOI	10.1109/ICMIRA.2013.69
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Fault tolerance Reversible Logic Fault tolerant systems Logic gates Constant inputs Vectors ALU Quantum cost Circuit faults Adders Garbage outputs
Content Type	Text
Resource Type	Article

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