NDLI: Parallel multiplier-accumulator based on radix-2 modified Booth algorithm by using a VLSI architecture

Content Provider	IEEE Xplore Digital Library
Author	Sathya, A. Fathimabee, S. Divya, S.
Copyright Year	2014
Description	Author affiliation: Dept. of ECE, Mailam Eng. Coll., Mailam, India (Sathya, A.; Fathimabee, S.; Divya, S.)
Abstract	In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delayed in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1's-complement-based radix-2 modified Booth's algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 /xm, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai's alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expert that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.
Starting Page	1
Ending Page	5
File Size	2125420
Page Count	5
File Format	PDF
e-ISBN	9781479923205
DOI	10.1109/ECS.2014.6892605
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-02-13
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer arithmetic Digital signal processing(DSP) Multiplier-and-accumulator (MAC) Very large scale integration Discrete wavelet transforms CMOS integrated circuits Booth multiplier Carry save adder (CSA) tree Adders Clocks
Content Type	Text
Resource Type	Article

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