NDLI: Fast modeling technique for nano scale CMOS inverter and propagation delay estimation

Content Provider	IEEE Xplore Digital Library
Author	Rjoub, A. Ahmad, A.
Copyright Year	2014
Description	Author affiliation: Comput. Eng. Dept., Jordan Univ. of Sci. & Technol., Irbid, Jordan (Rjoub, A.; Ahmad, A.)
Abstract	this paper proposes a new approach for designing the output waveform nanoscale CMOS inverter using the unit step input. The output waveform is obtained by solving the corresponding differential equations of the circuit. Various phenomena due to Short Channel Effects are included in the equation to achieve more accurate model. Based on this model, the propagation delay time for the input is estimated and used to get the ramp input propagation delay based on its deviation with step input propagation delay. This method is used to avoid the overhead in the CPU execution time during simulation process for huge number of inverters. The evaluations of the proposed model results give very good agreement when compared with BSIM4 level 54 model using HSPICE.
Starting Page	1
Ending Page	4
File Size	792358
Page Count	4
File Format	PDF
ISBN	9781479954124
DOI	10.1109/PATMOS.2014.6951891
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-29
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Drain-Induced Barrier Lowering(DIBL) Mobility Degradation Computational modeling Computer crashes Accuracy Handheld computers Velocity Saturation Logic gates Channel Length Modulation Transistors IP networks Propagation Delay(Pd) Unit Step Waveform
Content Type	Text
Resource Type	Article

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