NDLI: Parametric yield optimization using leakage-yield-driven floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Yang Xu Bo Wang Teich, J.
Copyright Year	2014
Description	Author affiliation: Univ. of Erlangen-Nuremberg, Erlangen, Germany (Yang Xu; Bo Wang; Teich, J.)
Abstract	Continuous process scaling has resulted in ever increasing process variations, which in turn cause severe parametric yield loss, e.g., timing & leakage yield loss. State-of-the-art methods optimize the leakage yield either by applying dual-vt or gate sizing technologies or by exploring the interdependency between leakage power and operating temperature. In this paper, we propose a novel leakage yield optimization method from another perspective, i.e., by exploring spatial correlations between leakage power of different modules. In our method, a very fast hierarchical leakage yield calculation method is introduced and integrated into a simulated annealing based floorplanner to build a leakage-yield-driven floorplanner, which can identify floorplans with optimized leakage yield. Experimental results show that our method significantly speeds up the leakage yield calculation by up to six orders of magnitude and the standard deviation of leakage can be reduced by up to 29% by applying our leakage-yield-driven floorplanning.
Starting Page	1
Ending Page	6
File Size	292595
Page Count	6
File Format	PDF
ISBN	9781479954124
DOI	10.1109/PATMOS.2014.6951860
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-29
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Correlation Logic gates Benchmark testing Random variables Approximation methods Optimization Principal component analysis
Content Type	Text
Resource Type	Article

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