NDLI: Optimization on cell-library design for digital Application Specific Printed Electronics Circuits

Content Provider	IEEE Xplore Digital Library
Author	Llamas, M. Mashayekhi, M. Carrabina, J. Matos, J. Reis, A.
Copyright Year	2014
Description	Author affiliation: CAIAC Group, Univ. Autonoma de Barcelona, Bellaterra, Spain (Llamas, M.; Mashayekhi, M.; Carrabina, J.) \|\| Inst. de Inf., UFRGS - Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil (Matos, J.; Reis, A.)
Abstract	This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells - either NAND2, NOR2 and inverters or NAND, NAND3 and inverters - performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well.
Starting Page	1
Ending Page	6
File Size	944588
Page Count	6
File Format	PDF
ISBN	9781479954124
DOI	10.1109/PATMOS.2014.6951885
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-29
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic synthesis ASPEC Technology mapping Very large scale integration Routing Optimization Standard Cell MOS devices ASIC OTFT Logic gates Libraries Transistor count Integrated circuit modeling Printed Electronics
Content Type	Text
Resource Type	Article

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