NDLI: Efficient lists intersection by CPU-GPU cooperative computing

Content Provider	IEEE Xplore Digital Library
Author	Di Wu Fan Zhang Naiyong Ao Gang Wang Xiaoguang Liu Jing Liu
Copyright Year	2010
Description	Author affiliation: Nankai-Baidu Joint Lab, College of Information Technical Science, Nankai University, Weijin Road 94, Tianjin, 300071, China (Di Wu; Fan Zhang; Naiyong Ao; Gang Wang; Xiaoguang Liu; Jing Liu)
Abstract	Lists intersection is an important operation in modern web search engines. Many prior studies have focused on the single-core or multi-core CPU platform or many-core GPU. In this paper, we propose a CPU-GPU cooperative model that can integrate the computing power of CPU and GPU to perform lists intersection more efficiently. In the so-called synchronous mode, queries are grouped into batches and processed by GPU for high throughput. We design a query-parallel GPU algorithm based on an element-thread mapping strategy for load balancing. In the traditional asynchronous model, queries are processed one-by-one by CPU or GPU to gain perfect response time. We design an online scheduling algorithm to determine whether CPU or GPU processes the query faster. Regression analysis on a huge number of experimental results concludes a regression formula as the scheduling metric. We perform exhaustive experiments on our new approaches. Experimental results on the TREC Gov and Baidu datasets show that our approaches can improve the performance of the lists intersection significantly.
Starting Page	1
Ending Page	8
File Size	232705
Page Count	8
File Format	PDF
ISBN	9781424465330
e-ISBN	9781424465347
DOI	10.1109/IPDPSW.2010.5470886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Multicore processing Query processing Search engines Load management Central Processing Unit Delay Web search Graphics processing unit
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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