NDLI: Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware

Content Provider	IEEE Xplore Digital Library
Author	Ziermann, T. Teich, J.
Copyright Year	2010
Description	Author affiliation: Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany (Ziermann, T.; Teich, J.)
Abstract	With the ongoing development of new FPGA generations, the reconfiguration time decreases and therefore the benefit of runtime reconfiguration increases. In this paper, we describe how to use runtime reconfiguration to improve the efficiency of transmitting streaming data on a communication channel shared with real-time applications. This means, the bandwidth that the streaming data has available is dynamically changing. To use the bandwidth effectively, different modules can be loaded on the reconfigurable hardware. These modules have a tradeoff between bandwidth and area requirements. The target now is to find an optimal reconfiguration schedule that minimizes an objective function consisting of two conflicting objectives: reducing the average area needed and providing a certain quality of transmission. In this paper, a model for this scheduling problem is presented and an Integer Linear Programming (ILP) formulation is introduced to calculate an optimal offline solution for benchmarking. In addition, an online scheduling system is presented. It uses the current delay of the streaming application to calculate the schedule. Extensive simulations have been made to show the benefits of the proposed solution.
Starting Page	1
Ending Page	4
File Size	408572
Page Count	4
File Format	PDF
ISBN	9781424465330
e-ISBN	9781424465347
DOI	10.1109/IPDPSW.2010.5470738
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adaptive scheduling Runtime Processor scheduling Bandwidth Computer architecture Cameras Displays Hardware Application software Field programmable gate arrays
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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