NDLI: Lower error floor of LDPC codes based on trapping sets elimination

Content Provider	IEEE Xplore Digital Library
Author	Le Dong Ziyu Zhao Jing Lei Er-bao Li
Copyright Year	2014
Description	Author affiliation: Coll. of Electron. Sci. & Eng., Nat. Univ. of Defense Technol., Changsha, China (Le Dong; Ziyu Zhao; Jing Lei; Er-bao Li)
Abstract	LDPC codes with excellent performance have great potential in applications of wireless mobile communications. However, the error floor phenomenon existing in LDPC codes limits its further application in disk storage and deep-space communications which require very low bit error rate (BER) system. The researchers find that trapping sets are the major reason why the LDPC codes have error floor. In this paper, we proposed an elimination algorithm to reduce small trapping sets. It was applying node rearrangement method to optimize the neighborhood of target nodes. In this way, cycles will be broken and the small size of trapping sets can be eliminated. The experimental results show that it can lower the error floor to improve the performance of LDPC codes. Besides, we also can keep the degree distribution, code rates and girth features of the original code with this method.
Starting Page	1
Ending Page	5
File Size	354093
Page Count	5
File Format	PDF
ISBN	9781479973392
DOI	10.1109/WCSP.2014.6992175
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Elimination algorithm Error floor Bit error rate Low-density parity check(LDPC) codes Charge carrier processes Trapping sets Decoding Structure optimization Floors Iterative decoding Optimization
Content Type	Text
Resource Type	Article

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