NDLI: Two-Bit Bit Flipping Algorithms for LDPC Codes and Collective Error Correction

Content Provider	IEEE Xplore Digital Library
Author	Dung Viet Nguyen Vasic, B.
Copyright Year	1972
Abstract	A new class of bit flipping algorithms for low-density parity-check codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.
Starting Page	1153
Ending Page	1163
Page Count	11
File Size	452208
File Format	PDF
ISSN	00906778
Volume Number	62
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Decoding Iterative decoding Charge carrier processes Parity check codes Error correction codes trapping set Bit flipping algorithms low-density parity-check codes error floor
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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