NDLI: Exploring dynamically reconfigurable multicore designs with NoRC designer

Content Provider	IEEE Xplore Digital Library
Author	Nunez-Yanez, J. Beldachi, A. Nabina, A. Hosseinabady, M.
Copyright Year	2012
Description	Author affiliation: Department of Electronic Engineering, University of Bristol, UK (Nunez-Yanez, J.; Beldachi, A.; Nabina, A.) \|\| Department of Electronic Engineering, Queens University Belfast, UK (Hosseinabady, M.)
Abstract	This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes in application requirements, operating conditions and/or process variations. The NoRC system is oriented at avoiding any centralized control with functions mapped to tiles at runtime depending on processing capabilities and location. The dynamic nature of the platform means that following a request for an application from an external host any idle tile can be configured as a master able to make additional requests to nearby tiles or as a slave able to service the requests. NoRC designer is used in this paper to investigate possible task mapping strategies suitable for this type of adaptive platform and also the power and partial reconfiguration overheads of commercial FPGAs.
Starting Page	254
Ending Page	260
File Size	2427199
Page Count	7
File Format	PDF
ISBN	9781467323598
e-ISBN	9781467323628
DOI	10.1109/HPCSim.2012.6266921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-02
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Program processors Tiles Heuristic algorithms Mapping and scheduling of tasks in NoCs Tools for designs space exploration of reconfigurable NoCs Hardware Voltage control Field programmable gate arrays Power and performance evaluation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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