NDLI: Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration

Content Provider	IEEE Xplore Digital Library
Author	Ito, K. Saen, M. Osada, K. Kodama, T. Mizuno, H.
Copyright Year	2010
Description	Author affiliation: Association of Super-Advanced Electronics Technologies (ASET), 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan (Ito, K.; Saen, M.; Osada, K.) \|\| Central Research Laboratory, Hitachi, Ltd., 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan (Kodama, T.; Mizuno, H.)
Abstract	In this paper, two designs of a 3D interconnection architecture for stacked processor-memory large-scale integrations (LSIs) were investigated. With consideration given to stacking formation, a hierarchical 3D interconnection architecture with a tightly coupled processor-memory stacking configuration is proposed for achieving both higher throughput per unit area and lower power consumption in the vertical communications. Compared with a baseline stacking configuration, the proposed architecture has the 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%. The performances of three-dimensional stacking chips with 64-processor cores are also estimated. As a result, the proposed architecture achieves twenty-times-lower power consumption of inter-chip communications than conventional 2D integration. A uni-directional interconnect configuration and a 3D two-way flow-control protocol were also developed to achieve maximal utilization of the 3D interconnection network. According to simulations using a cycle-accurate stacking LSI model, the proposed technique achieves 90% utilization of the interconnection network, while a conventional design achieves less than 60%.
Starting Page	1
Ending Page	6
File Size	456243
Page Count	6
File Format	PDF
ISBN	9781457705267
e-ISBN	9781457705274
DOI	10.1109/3DIC.2010.5751440
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-16
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Stacking Integrated circuit interconnections Throughput Three dimensional displays Large scale integration System-on-a-chip
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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