NDLI: COOL interconnect low power interconnection technology for scalable 3D LSI design

Content Provider	IEEE Xplore Digital Library
Author	Chacin, M. Uchida, H. Hagimoto, M. Miyazaki, T. Ohkawa, T. Ikeno, R. Matsumoto, Y. Imura, F. Suzuki, M. Kikuchi, K. Nakagawa, H. Aoyagi, M.
Copyright Year	2011
Description	Author affiliation: National Institute of Advanced Industrial Science and Technology 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan (Imura, F.; Suzuki, M.; Kikuchi, K.; Nakagawa, H.; Aoyagi, M.) \|\| TOPS Systems Corporation, Tsukuba Mitsui Building 5F, 1-6-1 Takezono, Tsukuba, Ibaraki 305-0032, Japan (Chacin, M.; Uchida, H.; Hagimoto, M.; Miyazaki, T.; Ohkawa, T.; Ikeno, R.; Matsumoto, Y.)
Abstract	3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher scalability in its functionality and performance just by increasing the number/type of chips, allows to be manufactured with much more flexibility, and has a better cost/performance than conventional 2D SoC based designs.
Starting Page	1
Ending Page	3
File Size	540380
Page Count	3
File Format	PDF
ISBN	9781612848839
e-ISBN	9781612848846
e-ISBN	9781612848822
DOI	10.1109/COOLCHIPS.2011.5890921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-20
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Distributed processing Microprocessors Integrated circuit interconnections Computer architecture Three dimensional displays Large scale integration 3D staked LSI Heterogeneous multi core Inter chip connection Driver circuits Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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