NDLI: Top-down and bottom-up multi-level cache analysis for WCET estimation

Content Provider	IEEE Xplore Digital Library
Author	Zhenkai Zhang Koutsoukos, X.
Copyright Year	2015
Description	Author affiliation: Vanderbilt Univ., Nashville, TN, USA (Zhenkai Zhang; Koutsoukos, X.)
Abstract	In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidation of memory blocks at higher cache levels. In order to ensure safety, analysis of cache hierarchies with inclusive caches for worst-case execution time (WCET) estimation is typically based on conservative decisions. Thus, the estimation may not be tight. In order to tighten the estimation, this paper proposes an approach that can more precisely analyze the behavior of a cache hierarchy maintaining the inclusion property. We illustrate the approach in the context of multi-level instruction caches. The approach first analyzes all the inclusive caches in the hierarchy in a bottom-up direction, and then analyzes the remaining non-inclusive caches in a top-down direction. In order to capture the inclusion victims and their effects, we also propose a concept of aging barrier and integrate it with the traditional must and persistence analyses to safely slow down their aging process so as to derive more precise analyses. We evaluate the proposed approach on a set of benchmarks and the evaluation reveals that the estimations are tightened.
Starting Page	24
Ending Page	36
File Size	851438
Page Count	13
File Format	PDF
ISBN	9781479986033
DOI	10.1109/RTAS.2015.7108413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Upper bound Estimation Aging Maintenance engineering Concrete Safety
Content Type	Text
Resource Type	Article

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