NDLI: Evaluation of Rodinia Codes on Intel Xeon Phi

Content Provider	IEEE Xplore Digital Library
Author	Misra, G. Kurkure, N. Das, A. Valmiki, M. Das, S. Gupta, A.
Copyright Year	2013
Description	Author affiliation: Centre for Dev. of Adv. Comput., HPC Solutions, Pune, India (Misra, G.; Kurkure, N.; Das, A.; Valmiki, M.; Das, S.; Gupta, A.)
Abstract	High performance computing (HPC) is a niche area where various parallel benchmarks are constantly used to explore and evaluate the performance of Heterogeneous computing systems on the horizon. The Rodinia benchmark suite, a collection of parallel programs is one of them. These parallel programs allow measuring the performance of emerging heterogeneous computing architectures that consists of both, many core CPUs and accelerators such as GPUs. Intel's x86-based 'Many Integrated Core' (MIC) product "Xeon Phi" is one such architecture, which is developed to enhance the speed, performance and computing capability. Advanced architecture such as Intel's Many Integrated Core has revolutionized the HPC landscape by combining many Intel CPU cores onto a single chip. The paper addresses performance of two Rodinia kernels "LUD" and "HotSpot" when executed in "native mode" i.e. direct execution on Xeon Phi coprocessor and then offloaded by incorporating the offloading directives in the code to mobilize code segments from host (CPU) to Xeon Phi coprocessor. This paper also exhibits the performance of source code of LUD and Hotspot, in terms of execution time measured on Intel Xeon Phi architecture and on CPU as well.
Sponsorship	IEEE Region 10 - Asia Pacific
Starting Page	415
Ending Page	419
File Size	598321
Page Count	5
File Format	PDF
ISBN	9781467356534
ISSN	21660662
DOI	10.1109/ISMS.2013.118
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-29
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing High Performance Computing Scalability Intel Xeon Phi Benchmark testing Rodinia Benchmark Matrix decomposition Kernel Heterogeneous Computing. Coprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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