NDLI: Energy efficient encoding technique for data-bus in DSM technology

Content Provider	IEEE Xplore Digital Library
Author	Sathish, A. Latha, M.M. Kishore, K.L. Reddy, Y.P.K.
Copyright Year	2011
Description	Author affiliation: Dept of ECE, RGMCET, Nandyal, A.P., India (Sathish, A.; Latha, M.M.) \|\| Dept of ECE, J.N.T.University, Hyderabad, A.P, India (Kishore, K.L.; Reddy, Y.P.K.)
Abstract	As CMOS VLSI integration continues with shrinking feature size the energy dissipation on the on-chip data buses becoming a bottle neck for high performance integrated circuits. Coupling capacitance of the on-chip data buses and interconnects plays an important role in the reliability of the system. In many digital processors and SoC the energy dissipation on the data buses and interconnects is a major part of the total chip power dissipation. This major part of the energy dissipation is due to the self and coupling transitions occurring on the data bus and interconnects when signals are transmitted. Reducing these transitions is an important design factor. Hence reducing transitions can reduce energy dissipation. One of the best techniques to reduce the transitions is to encode the data on the data bus. Hence an efficient data bus encoding scheme is proposed which can reduce the energy dissipation due to transitions. The proposed technique can able to reduce the energy dissipation by 44% to 47% and 40% to 44% for 8-bit and 16-bit data bus respectively compare to unencoded data.
Starting Page	490
Ending Page	492
File Size	661400
Page Count	3
File Format	PDF
ISBN	9781612846545
e-ISBN	9781612846538
DOI	10.1109/ICSCCN.2011.6024600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VDSM Self transitions Hamming distance Interconnects Crosstalk SoC Encoding Couplings Data buses Wires Energy dissipation Coupling transitions Capacitance Power dissipation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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