NDLI: Power reduction using DVFS with a producer-consumer FIFO

Content Provider	IEEE Xplore Digital Library
Author	Pillamari, P. Naidu, K.J. Kittur, H.M.
Copyright Year	2011
Description	Author affiliation: School of Electronics Engineering, VIT University, Vellore, India (Naidu, K.J.; Kittur, H.M.) \|\| M.Tech VLSI Design, School of Electronics Engineering, VIT University, Vellore, India (Pillamari, P.)
Abstract	Power management has become a critical design parameter as more transistors are integrated on a single chip. Lowering the supply voltage is one of the attractive approaches to save power of the variable workload system, and to achieve long battery life. DVFS is one of the efficient techniques to reduce the energy consumption. The main idea behind DVFS scheme is to dynamically scale the supply voltage of CPU, to provide enough circuit speed to process the system workload in order to meet the time and performance, thereby reducing power. In this paper, we consider a Network on Chip (NoC) architecture partitioned into Voltage Frequency Island (VFI). Our challenge is to determine which voltage and clock values support the VFI, depending on the workload. For calculating the workload of a VFI, a producer-consumer FIFO is introduced. The introduced architecture is to reduce the complexity and the total power consumption. The proposed methodology is implemented with TSMC 90nm technology using Cadence Compiler, and it reduces power consumption by 32.2% for a NoC.
Starting Page	454
Ending Page	458
File Size	684700
Page Count	5
File Format	PDF
ISBN	9781612846545
e-ISBN	9781612846538
DOI	10.1109/ICSCCN.2011.6024593
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Power demand Signal processing algorithms Clustering algorithms Computer architecture Prediction algorithms Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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