NDLI: Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm

Content Provider	IEEE Xplore Digital Library
Author	Raza, B. Parvez, H. Mohiuddin, M.
Copyright Year	2014
Description	Author affiliation: Karachi Inst. of Econ. & Technol., Karachi, Pakistan (Raza, B.; Parvez, H.; Mohiuddin, M.)
Abstract	Simulated Annealing (SA) algorithm is widely employed to achieve optimal placement solution for FPGAs. However, it attempts a notably large number of placement moves on each temperature step, thus increasing the placement runtime considerably. The work presented in this paper reduces the placement runtime by intelligently reducing the total number of placement moves attempted on each temperature step. We have proposed four alternate formulas for calculating the number of moves that must be attempted per temperature step. Empirical study shows that our proposed formulas have achieved up to 2.1 times reduction in placement runtime without compromising placement quality.
Starting Page	1
Ending Page	5
File Size	377261
Page Count	5
File Format	PDF
ISBN	9781479958108
DOI	10.1109/ReCoSoC.2014.6860685
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Schedules Runtime Design automation Simulated Annealing Fast Placement Trade-off Placement cost versus Time Placement quality Arrays Field programmable gate arrays Standards
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hardware-assisted simulated annealing with application for fast FPGA placement

3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems

Replace: An incremental placement algorithm for field programmable gate arrays

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Fast timing driven placement using tabu search

Fast FPGA placement algorithm using Quantum Genetic Algorithm with Simulated Annealing

Optimization of uncertain construction time-cost trade off problem using simulated annealing algorithm

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Enhancing timing-driven FPGA placement for pipelined netlists

Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm

Similar Documents

Hardware-assisted simulated annealing with application for fast FPGA placement

3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems

Replace: An incremental placement algorithm for field programmable gate arrays

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Fast timing driven placement using tabu search

Fast FPGA placement algorithm using Quantum Genetic Algorithm with Simulated Annealing

Optimization of uncertain construction time-cost trade off problem using simulated annealing algorithm

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Enhancing timing-driven FPGA placement for pipelined netlists

Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm