NDLI: Monitoring communication channels on a shared memory multi-processor system on chip

Content Provider	IEEE Xplore Digital Library
Author	Genius, D. Pouillon, N.
Copyright Year	2011
Description	Author affiliation: LIP6, Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France (Genius, D.; Pouillon, N.)
Abstract	To meet performance requirements, streaming applications have been mapped to Multi-Processor System on Chip (MPSoC). The Kahn Process Network (KPN) paradigm is sufficient when dealing with pipeline parallelism, but such point-to-point channels are impractical in the presence of massive task farm parallelism. Multi Writer Multi Reader (MWMR) channels generalize KPN in such a way that multiple writers and multiple readers access the same channel. They are implemented as software channels stored in on-chip memory to accommodate access by hardware and software tasks alike. The price to pay for this implementation is increased traffic to and from memory. Typical representatives are telecommunication applications which may treat hundreds or thousands of flows at a time, where the same chain of treatments is applied to every packet. The latency for this treatment depends on the packet's content, and can thus not be foreseen. Among multiple tasks which access a MWMR channel, the time to obtain a lock is variable. In consequence, fill states of MWMR channels vary heavily and it is crucial to monitor it in order to detect potential bottlenecks. We show how this can be done early in the design process by using SoCLib/DSX.
Starting Page	1
Ending Page	8
File Size	446644
Page Count	8
File Format	PDF
ISBN	9781457706400
e-ISBN	9781457706424
DOI	10.1109/ReCoSoC.2011.5981502
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Throughput Hardware Software Communications technology System-on-a-chip Coprocessors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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