NDLI: A graph based algorithm to minimize total wire length in VLSI channel routing

Content Provider	IEEE Xplore Digital Library
Author	Sau, S.S. Pal, A. Mandal, T.N. Datta, A.K. Pal, R.K. Chaudhuri, A.
Copyright Year	2011
Description	Author affiliation: Department of Information Technology, School of Technology, Assam University, Silchar, Cachar - 788 011, India (Pal, R.K.) \|\| Department of Computer Science, Sammilani Mahavidyalaya, Baghajatin, Kolkata - 700 075, West Bengal, India (Sau, S.S.) \|\| Department of Computer Science and Engineering, Jadavpur University, Kolkata - 700 032, West Bengal, India (Chaudhuri, A.) \|\| Department of Computer and System Sciences, Visva-Bharati, Santiniketan, Birbhum -731 235, West Bengal, India (Datta, A.K.) \|\| Harinavi Subhasini Balika Sikshalaya, PO: Harinavi, 24 Parganas (South) - 743 359, West Bengal, India (Pal, A.) \|\| IBM Pvt Ltd, DLF IT Park, Tower B, 3rd Floor, Rajarhat, 24 Parganas (North), Kolkata - 700 156, West Bengal, India (Mandal, T.N.)
Abstract	Minimization of total (vertical) wire length is one of the most important problems in laying out blocks in VLSI physical design. Minimization of wire length not only reduces the cost of physical wiring required, but also reduces the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg, two-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as low total (vertical) wire length as possible. In this paper we develop an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model. Experimental results obtained are greatly encouraging.
Starting Page	61
Ending Page	65
File Size	145920
Page Count	5
File Format	PDF
ISBN	9781424487271
e-ISBN	9781424487288
DOI	10.1109/CSAE.2011.5952634
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-10
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Constraints and constraint graphs Wire length minimization No-doglegging Reserved layer model Clique Manhattan routing Parametric difference of net Algorithm VLSI channel routing problem
Content Type	Text
Resource Type	Article

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