NDLI: Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique

Content Provider	IEEE Xplore Digital Library
Author	Nakano, D. Kohda, Y. Takano, K. Yamane, T. Ohba, N. Katayama, Y.
Copyright Year	2011
Description	Author affiliation: IBM Research - Tokyo, 1623-14 Shimo-tsuruma, Yamato, Kanagawa 242-8502 Japan (Nakano, D.; Kohda, Y.; Takano, K.; Yamane, T.; Ohba, N.; Katayama, Y.)
Abstract	We describe a multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique. To realize low-power operation at such a high data rate, it is crucial to design the system with reduced oversampling factor and bit depth. A table-based IQ phase rotator and a time-domain polyphase equalizer have been designed for realizing a robust and low-power coherent link under these conditions with rounding-error-free operations and effective interpolations. The entire baseband signal processing is implemented in FPGAs and we are successful in multi-Gbps per-packet transmissions per the IEEE 802.15.3c single-carrier PHY (SC-PHY) format for π/2-BPSK and π/2-QPSK modulations at a full data rate. We confirmed that the 60-GHz single-carrier system can be robust to the carrier and sampling frequency offsets within 50 ppm, even with 2× oversampling factor and 3-bit ADCs, which can lower the power consumption.
Starting Page	1
Ending Page	3
File Size	366667
Page Count	3
File Format	PDF
ISBN	9781612848839
e-ISBN	9781612848846
e-ISBN	9781612848822
DOI	10.1109/COOLCHIPS.2011.5890929
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-20
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband Power demand Adaptive filters Time-domain equalizer Coherence Adaptive equalizers Time domain analysis Single carrier Low-power Field programmable gate arrays Coherent detection Millimeter wave
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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