NDLI: Synthesis and comparison of low-power high-throughput architectures for SAD calculation

Content Provider	IEEE Xplore Digital Library
Author	Walter, F.L. Diniz, C.M. Bampi, S.
Copyright Year	2011
Description	Author affiliation: GME - PGMICRO Graduate Programe on Microelectronics - Informatics Institute, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre - Brazil (Walter, F.L.; Diniz, C.M.; Bampi, S.)
Abstract	This paper presents the standard-cells synthesis and comparison of parallel hardware architectures for the Sum of Absolute Differences (SAD) datapath, focusing on different design points such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (isoperformance target). Clock gating and different combination of parallelism and pipeline architectural techniques were explored in this work. In order to generate the results, we used the TSMC 0.18 µm standard-cells library with standard, slow and fast cells, and the back-end Cadence tools, e.g. Power Analysis, for the power measurements. We achieved significant power reduction for the architectures with low-frequency and high parallelism, slow cells and mainly with only one pipeline stage.
Starting Page	1
Ending Page	4
File Size	443232
Page Count	4
File Format	PDF
ISBN	9781424494842
e-ISBN	9781424494859
DOI	10.1109/LASCAS.2011.5750276
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-23
Publisher Place	Colombia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Pipelines Computer architecture Parallel processing Throughput Power dissipation Sum of Absolute Differences (SAD) Low-power Clocks Isoperformance
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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