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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lolas, C.Z. Soudris, D. Karafyllidis, I. Thanailakis, A. |
| Copyright Year | 1999 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece (Lolas, C.Z.) |
| Abstract | A new approach for implementing low power array architectures based on energy recovery techniques (i.e. adiabatic switching) is introduced. The main principles of the reversible pipeline are adopted. However, its large hardware complexity does not allow efficient implementations. Exploiting the inherent property of a reversible pipeline system that the "reverse" logic blocks are used in different time instances and the characteristic that several applications have identical logic blocks, we can reduce the hardware complexity significantly. Here, emphasis is given to the hardware reduction and function of the proposed reversible pipeline architectures. Using an appropriate multiplexer and clocking strategy, we can achieve the reversible operation with small hardware cost. The proposed approach is suitable for implementing array processor architectures, which realize a certain class of Digital Signal Processing (DSP) applications. |
| Starting Page | 795 |
| Ending Page | 798 |
| File Size | 338063 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780356829 |
| DOI | 10.1109/ICECS.1999.813228 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-09-05 |
| Publisher Place | Cyprus |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pipelines Logic Hardware Clocks Computer architecture Digital signal processing Design methodology Circuits Capacitance Throughput |
| Content Type | Text |
| Resource Type | Article |
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