NDLI: Implementation of sum of absolute difference using optimized partial summation term reduction

Content Provider	IEEE Xplore Digital Library
Author	Shah, N.N. Agarwal, K.R. Singapuri, H.M.
Copyright Year	2013
Description	Author affiliation: Electron. & Commun. Eng. Dept, Sarvajanik Coll. of Eng. & Technol., Surat, India (Shah, N.N.; Agarwal, K.R.; Singapuri, H.M.)
Abstract	Video has vast application domains like medicine, security and surveillance. Video coding can be implemented in both hardware and software technologies in which both quality and controllability are required. Process of determining motion vectors known as motion estimation (ME) is a fundamental step in the extraction of activity in videos. The Block Matching Algorithm (BMA) based motion estimation is the most popular method in which the distance measurement between objects in consecutive frame can be computed based on matching criterions called cost function which computes the distortion between the blocks. The massive computations associated with block matching prevent software implementations from running in real-time and lead towards hardware implementation. Due to simplicity in hardware implementation, SAD is preferred cost function in block matching. Several architectures using Sum of Absolute difference (SAD) are developed to improve the hardware efficiency and computational speed of block-matching algorithms. This paper gives comparative analysis of area and speed of operation for Sequential, Pipeline and Parallel architectures for SAD implementation. Parallel architecture provides best throughput at the cost of highest resource utilization. For performing absolute difference (AD) and summation, adder and carry propagate mechanisms are required. In this paper optimized architecture for accumulation of computed AD in Parallel architecture is presented using partial summation term reduction technique which reduces adders by 40% and improve speed of operation around 12% to 43% for various FPGA families.
Starting Page	192
Ending Page	196
File Size	357963
Page Count	5
File Format	PDF
ISBN	9781479914395
e-ISBN	9781479914418
DOI	10.1109/ICAES.2013.6659390
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Macroblock(MB) Pipelines Sum of Absolute Difference(SAD) Processing Element(PE) Parallel architectures Delays High definition video Adders Clocks Block Matching Algorithm(BMA)
Content Type	Text
Resource Type	Article

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