NDLI: Design of Ternary Content Addressable Memory (TCAM) with 180 nm

Content Provider	IEEE Xplore Digital Library
Author	Kumar, S. Noor, A. Kaushik, B.K. Kumar, B.
Copyright Year	2011
Abstract	This paper deals with the design and analysis of Ternary Content Addressable Memory using 180nm technology. The main aim of the TCAM is to perform the search operation using match line (ML). Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. TCAMs are popular because of their searching operation based on the content unlike the RAM cell which does it on the basis of address. The main contribution of this work is testing of ML. The testing of match line was a task which needs to be done to check the searching condition in the TCAM cell. To accomplish this task a new circuitry was added to the existing circuit in order to test the masking condition in a TCAM cell. The work was started from the scratch. First a RAM cell was designed with the goal in mind to be used for the TCAM cell. Various parameters were calculated for the stability of a SRAM cell. The SRAM cell designed was then used in the design of Binary CAMs. After the completion of binary CAM, the cell was modified into the TCAM cell. The additional circuitry added was used to test the working of match line during the search operation of the TCAM cell. Finally, design and testing of a complete TCAM cell is presented.
Starting Page	1
Ending Page	5
File Size	278699
Page Count	5
File Format	PDF
ISBN	9781424491896
e-ISBN	9781424491902
DOI	10.1109/ICDECOM.2011.5738528
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-24
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Associative memory Computer aided manufacturing Noise Random access memory Routing Internet Transistors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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