NDLI: Efficient implementation of fast convolution in ASIP

Content Provider	IEEE Xplore Digital Library
Author	Venkatesan, A. Kumar, S.V.
Copyright Year	2010
Description	Author affiliation: Anna University, Chennai, India (Kumar, S.V.) \|\| Easwari Engineering College, Anna University, Chennai, India (Venkatesan, A.)
Abstract	In this paper various approaches of implementing a hardware efficient fast convolution have been discussed. Long length convolutions implemented on a FPGA are not area, power efficient and also it cannot be implemented on a single FPGA. To increase the speed of long convolutions and to meet the calculation capacity of each single FPGA chip, the long coefficient sequence can be partitioned into short sub-sequences. Each short length convolution can then be made area efficient at the expense of decrease in speed by implementing them as a convolution ASIP. The asynchronous ASIP is still faster than a synchronous ASIP. The speed of an asynchronous convolution processor can be further increased by applying Algorithmic Strength Reduction (ASR) where the number of multiplications, (which is more time consuming than an addition) is alleviated at the expense of increase in the number of additions required in a convolution process. Several algorithms based on ASR which would lead to a faster convolution ASIP have been discussed.
Starting Page	203
Ending Page	207
File Size	473591
Page Count	5
File Format	PDF
ISBN	9781424491841
e-ISBN	9781424491834
DOI	10.1109/RSTSCC.2010.5712848
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-13
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Convolution Signal processing algorithms Polynomials Hardware VLIW Field programmable gate arrays
Content Type	Text
Resource Type	Article

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