NDLI: Mixed-Signal VLSI Design in 0.5µm Process of Nano-Power Subcompact Mirror-Amplifier for AccuSensor

Content Provider	IEEE Xplore Digital Library
Author	Chowdhury, I. Amin, R. Islam, S.M.K.N. Rahman, M.S. Binzaid, S.
Copyright Year	2011
Abstract	Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6μm layout and 0.5μm enhanced fabrication process. The improved design has area of 101?X48? (minimized from 126?X59?) or 30.3μmX15μm (minimized from 37.8μmX17.7μm) in 0.6?m CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tiny chip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.
Starting Page	522
Ending Page	526
File Size	693354
Page Count	5
File Format	PDF
ISBN	9781457720338
e-ISBN	9780769545875
DOI	10.1109/CICN.2011.112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mixed-Signal IC Compound Device Very large scale integration Inverters Dual Amplifier VLSI Design Fabrication Layout Precision Sensor Nano-Power Chip Detectors Logic gates CMOS integrated circuits Mirror-Amplifier Coincidence detector
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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