NDLI: A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

Content Provider	IEEE Xplore Digital Library
Author	Rousseau, B. Manet, P. Loiselle, I. Legat, J. Vandierendonck, H.
Copyright Year	2010
Description	Author affiliation: Ghent University, Dept. ELIS/HiPEAC, St.-Pietersnieuwstraat, 41, B-9000, Belgium (Vandierendonck, H.) \|\| Université catholique de Louvain (UCL), Laboratoire de microélectronique (DICE), Place du Levant, 3, B-1348, Louvain-la-Neuve, Belgium (Rousseau, B.; Manet, P.; Loiselle, I.; Legat, J.)
Abstract	The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.
Starting Page	273
Ending Page	280
File Size	680001
Page Count	8
File Format	PDF
ISBN	9781424487349
e-ISBN	9781424487356
e-ISBN	9781424487332
DOI	10.1109/DASIP.2010.5706275
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-26
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Microarchitecture Computer architecture Digital signal processing Homogeneous many-core Signal processing Timing Power efficiency VLIW Optimization Processor architecture
Content Type	Text
Resource Type	Article

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