NDLI: Compiling for EDGE architectures

Content Provider	IEEE Xplore Digital Library
Author	Smith, A. Burrill, J. Gibson, J. Maher, B. Nethercote, N. Yoder, B. Burger, D. McKinley, K.S.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., Texas Univ., Austin, TX, USA (Smith, A.)
Abstract	Explicit data graph execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks a program into a sequence of structured blocks that the hardware executes atomically. The instructions within each block communicate directly, instead of communicating through shared registers. The TRIPS EDGE architecture imposes restrictions on its blocks to simplify the microarchitecture: each TRIPS block has at most 128 instructions, issues at most 32 loads and/or stores, and executes at most 32 register bank reads and 32 writes. To detect block completion, each TRIPS block must produce a constant number of outputs (stores and register writes) and a branch decision. The goal of the TRIPS compiler is to produce TRIPS blocks full of useful instructions while enforcing these constraints. This paper describes a set of compiler algorithms that meet these sometimes conflicting goals, including an algorithm that assigns load and store identifiers to maximize the number of loads and stores within a block. We demonstrate the correctness of these algorithms in simulation on SPEC2000, EEMBC, and microbenchmarks extracted from SPEC2000 and others. We measure speedup in cycles over an Alpha 21264 on microbenchmarks.
Starting Page	11
Ending Page	195
File Size	501593
Page Count	185
File Format	PDF
ISBN	0769524990
DOI	10.1109/CGO.2006.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Concurrent computing Program processors Reduced instruction set computing Computer architecture Microarchitecture Delay VLIW Energy efficiency Pipeline processing
Content Type	Text
Resource Type	Article

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