NDLI: Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

Content Provider	IEEE Xplore Digital Library
Author	Jianjing Wang Chung, H.S.-H.
Copyright Year	2013
Description	Author affiliation: Center for Smart Energy Conversion & Utilization Res., City Univ. of Hong Kong, Hong Kong, China (Jianjing Wang; Chung, H.S.-H.)
Abstract	Limiting the spurious triggering pulse in the gate-source voltage of the lower MOSFET during the turn-on transition of the upper MOSFET is mandatory to prevent substantial switching loss and even shoot-through in the synchronous buck converter. This paper conducts an exhaustive investigation into the impact of the inherent parasitic elements on the spurious triggering pulse to facilitate a reliability-oriented design. An analytical model that considers the parasitic capacitances and inductances, reverse recovery characteristics of the body diode and the interaction between the upper and the lower MOSFETs is established to quantify this pulse. The spurious triggering pulse is found to stem from the induced increase in the gate voltage and the induced decrease in the source voltage. Variation in the magnitude of the spurious triggering pulse in regard to each parasitic element is identified accordingly. Experimental results of a practical synchronous buck converter affirm the theoretical analysis.
Starting Page	480
Ending Page	487
File Size	2650564
Page Count	8
File Format	PDF
ISBN	9781479903368
DOI	10.1109/ECCE.2013.6646740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Spurious turn-on MOSFET Parasitic elements Synchronous buck converter Switches Logic gates Capacitance Threshold voltage Mathematical model
Content Type	Text
Resource Type	Article

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