NDLI: Reducing instruction TLB's leakage power consumption for embedded processors

Content Provider	IEEE Xplore Digital Library
Author	Zhao Lei Hui Xu Ikebuchi, D. Amano, H. Sunata, T. Namiki, M.
Copyright Year	2010
Description	Author affiliation: Dept. of Computer Science, Tokyo University of Agriculture and Technology, Japan (Sunata, T.; Namiki, M.) \|\| Dept. of Computer Science and Information, Keio University, Yokohama, Japan (Zhao Lei; Hui Xu; Ikebuchi, D.; Amano, H.)
Abstract	This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage structure which stores the recent address-translation information, the TLB access frequency can be drastically decreased and the instruction TLB can be turned into the low leakage mode with the dual voltage supply technique. Based on such a design philosophy, three different implementation policies are proposed. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.
Starting Page	477
Ending Page	484
File Size	1150948
Page Count	8
File Format	PDF
ISBN	9781424476121
e-ISBN	9781424476152
DOI	10.1109/GREENCOMP.2010.5598277
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded processor Transform coding Ash Virtual private networks Kernel Leakage power Instruction TLB
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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