NDLI: Stretch and compress based re-scheduling techniques for minimizing the execution times of DAGs on multi-core processors under energy constraints

Content Provider	IEEE Xplore Digital Library
Author	King, D. Ahmad, I. Sheikh, H.F.
Copyright Year	2010
Description	Author affiliation: University of Texas at Arlington, Computer Science and Engineering, USA (King, D.; Ahmad, I.; Sheikh, H.F.)
Abstract	Given an initial schedule of a parallel program represented by a directed acyclic graph (DAG) and an energy constraint, the question arises how to effectively determine what nodes (tasks) can be penalized (slowed down) through the use of dynamic voltage scaling. The resulting re-schedule length with a strict energy budget should have a minimum amount of expansion compared to the original schedule achieved with full energy. We propose three static schemes that aim to achieve this goal. Each scheme encompasses submitting a schedule to either a conceptual “stretch” (starting tasks with a maximum voltage supplied to all cores followed by methodical voltage reductions) or “compress” (starting tasks with a minimum voltage supplied to all cores followed by methodical voltage boosts). The complexity arises due to the inter-dependence of tasks. We propose methods that efficiently make such findings by analyzing the DAG and determining the “impact factor” of a node in the graph for the purpose of guiding the schedule toward the desired goal. The comparison between the stretch-alone and compress-alone based algorithms leads to a third algorithm that employs schedule “compression,” but reschedules all cores following each successive voltage adjustment. Detailed simulation experiments demonstrate the effect of various task and processor parameters on the performance of the proposed algorithms.
Starting Page	49
Ending Page	60
File Size	1821988
Page Count	12
File Format	PDF
ISBN	9781424476121
e-ISBN	9781424476152
DOI	10.1109/GREENCOMP.2010.5598274
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Multi-core Variable speed drives Parallel processing Scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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