NDLI: Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors

Content Provider	IEEE Xplore Digital Library
Author	Petrov, P. Xiangrong Zhou
Copyright Year	2005
Description	Author affiliation: University of Maryland, College Park, MD (Petrov, P.; Xiangrong Zhou)
Abstract	In this paper we present an application-driven address translation scheme for low-power and real-time embedded processors with virtual memory support. The power inefficiency and nondeterministic execution times of address-translation mechanisms have been major barriers in adopting and utilizing the benefits of virtual memory in embedded processors with low-power and real-time constraints. To address this problem, we propose a novel, Customizable Translation Table (CTT) organization, where application knowledge regarding the virtual memory footprint is used in order to eliminate conflicts in the hardware translation buffer and, thus, achieve tag-free address translation lookups. The set of virtual pages is partitioned into groups, such that for each group only a few of the least significant bits are used as an index to obtain the physical page number. We outline an efficient compile-time algorithm for identifying these groups and allocate their translation entries optimally into the CTT. The proposed methodology relies on the combined efforts of compiler, operating system, and hardware architecture to achieve a significant power reduction. The experiments that we have performed on a set of embedded applications show power reductions in the range of 55% to 80% compared to a general- purpose Translation Lookaside Buffer (TLB).
Starting Page	33
Ending Page	38
File Size	150875
Page Count	6
File Format	PDF
ISBN	1595931619
DOI	10.1145/1084834.1084848
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Energy efficiency Hardware Virtual private networks Educational institutions Energy consumption Partitioning algorithms Operating systems Embedded system Memory management Kernel reconfigurability adaptable systems multi-mode synthesis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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