NDLI: Extending fault periodicity table for testing faults in memories under 20nm

Content Provider	IEEE Xplore Digital Library
Author	Harutyunyan, G. Shoukourian, S. Vardanian, V. Zorian, Y.
Copyright Year	2014
Description	Author affiliation: Synopsys, Armenia (Harutyunyan, G.; Shoukourian, S.; Vardanian, V.; Zorian, Y.)
Abstract	A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. In this paper, application of the proposed methodology for description of memory faults in technologies below 20nm, including 16/14nm FinFET-based memories, is shown. Specifically, it is shown that all recently discovered FinFET-specific faults successfully fit into FPT.
Starting Page	1
Ending Page	4
File Size	237915
Page Count	4
File Format	PDF
ISBN	9781479976300
DOI	10.1109/EWDTS.2014.7027088
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-26
Publisher Place	Ukraine
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Buildings Random access memory FinFET Built-in self-test Logic gates FinFETs Fault periodicity March test Complexity theory
Content Type	Text
Resource Type	Article

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