NDLI: A fast lock time pulsewidth control loop using second order passive loop filters

Content Provider	IEEE Xplore Digital Library
Author	Navidi, M. M. Abrishamifar, A.
Copyright Year	2011
Description	Author affiliation: Iran University of Science and Technology (Navidi, M. M.; Abrishamifar, A.) This paper presents a usage of the second order loop filters for PWCLs. The analysis shows that by using this kind of loop filters, lock time is much better than conventional PWCLs and is comparable with PWCLs using fast locking circuits. Also, power consumption of the PWCLs using second order filters are less than the fast locking PWCLs. A 0 18 um CMOS technology and 1.8 V supply voltage are used to verify the operation of the proposed circuit. The simulation results show that the proposed PWCL reduces the lock time to 405ns. The proposed PWCL operates from 400MHz to 1.4GHz. The duty cycle of the input clock is from 10% to 80% and the duty cycle of the output clock is from 30% to 60% in step of 10%. With an input clock operating at 1GHz lock time and power dissipation of the PWCL are 390ns and 0.187mW, respectively.
Starting Page	1
Ending Page	5
File Size	980181
Page Count	5
File Format	PDF
ISBN	9781457707308
e-ISBN	9789644634284
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-17
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	AmirKabir Univ of Tech
Subject Keyword	Charge pumps Passive filters Passive loop filters Transfer functions Time frequency analysis CMOS integrated circuits Duty cycle control Phase locked loops Pulsewidth Control Loop Clocks Lock-in time
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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