NDLI: Measurement and analysis of contact plug resistance variability

Content Provider	IEEE Xplore Digital Library
Author	Balakrishnan, K. Boning, D.
Copyright Year	2009
Description	Author affiliation: Microsystems Technology Laboratories, MIT, Cambridge, MA, USA (Balakrishnan, K.; Boning, D.)
Abstract	The impact of contacts on device and circuit performance is becoming larger with technology scaling because of higher resistance as well as increased variability. Thus, techniques are needed for measurement, analysis, and modeling of variation in contactss, and for devices, interconnects, and circuits in general, in order to ensure robust circuit design. A test chip for characterizing contact plug resistance variability is designed in a 90nm CMOS process. Each chip is capable of characterizing over 35,000 devices under test. Statistical analysis of the measurement results show that the contact plug resistance changes as a function of key layout parameters, such as the distance from the contact to the polysilicon gate and the distance from the contact to the edge of the diffusion region. Spatial variation analysis shows that the resistance distribution has a systematic die-to-die pattern, possibly caused by variability in the lithography process. Spatial correlation analysis is also performed to identify the possibility of additional systematic trends or separation-distance dependent correlated random variation. Results of these analyses motivate the need for both numerical and compact models for contacts which incorporate variability information.
Starting Page	415
Ending Page	422
File Size	854919
Page Count	8
File Format	PDF
ISBN	9781424440719
DOI	10.1109/CICC.2009.5280812
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrical resistance measurement Plugs Contact resistance Semiconductor device measurement Circuit testing Circuit optimization Semiconductor device modeling Integrated circuit interconnections Robustness Circuit synthesis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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