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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiao Yu Li Li Yuang Zhang Hongbing Pan Shuzhuan He |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electron. Sci. & Eng., Nanjing Univ., Nanjing, China (Xiao Yu; Li Li; Yuang Zhang; Hongbing Pan; Shuzhuan He) |
| Abstract | With the rapid development of the technology of 3D IC and Network-on-Chip (NoC) technology, 3D NoC emerged and drew more and more attention of researchers in recent years. But the issues of memory organization and power consumption have become two great challenges in the design of 3D NoC. This paper proposed three kinds of memory efficient 3D NoC architecture called core, corner and windows in order to achieve better performance and lower power consumption for the system. A simulation platform of 3D NoC is built with a systematical modeling language -SystemC to evaluate the performance. The experiment result shows that when compared with other two traditional 3D NoC memory architecture perlayer and mixed, two 3D NoC architectures we proposed can gain better performance and lower power consumption respectively. |
| Starting Page | 340 |
| Ending Page | 344 |
| File Size | 334420 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467347075 |
| ISSN | 19483449 |
| e-ISBN | 9781467347082 |
| DOI | 10.1109/ICCA.2013.6565107 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-06-12 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Power demand Program processors Memory management Delays Memory architecture Routing Organizations Memory Architecture Power Consumption Memory Efficient 3D NoC SystemC |
| Content Type | Text |
| Resource Type | Article |
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