NDLI: Network Properties and Latency of Triple-based Hierarchical Interconnection Netrwork

Content Provider	IEEE Xplore Digital Library
Author	Baojun Qiao Feng Shi Weixing Ji Hong Song
Copyright Year	2007
Description	Author affiliation: Beijing Inst. of Technol., Beijing (Baojun Qiao; Feng Shi; Weixing Ji; Hong Song)
Abstract	A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC (System-on-Chip). Triple-based Hierarchical Interconnection Network (THIN) was proposed that aims to decrease the node degree, reduce the links and shorten the diameter. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. In this paper, the network properties and zero-load latency are studied and compared with 2-D mesh. The compare results show that THIN is a better candidate for constructing the NOC than 2-D Mesh, when there are not too many nodes.
Starting Page	976
Ending Page	979
File Size	686298
Page Count	4
File Format	PDF
ISBN	9781424408177
DOI	10.1109/ICCA.2007.4376501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Network-on-a-chip Network topology System-on-a-chip Multiprocessor interconnection networks Computer science Chip scale packaging Bandwidth Automatic control Control systems network properties interconnection architecture network-on-chip network topology
Content Type	Text
Resource Type	Article

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