NDLI: ATM LAN interconnections with a cut-through nonblocking switch

Content Provider	IEEE Xplore Digital Library
Author	Tsang-Ling Sheu
Copyright Year	1995
Description	Author affiliation: IBM Corp., Research Triangle Park, NC, USA (Tsang-Ling Sheu)
Abstract	The paper presents a cut through ATM switch with shared buffers for LAN interconnections. The incoming ATM cells are not stored into shared buffers as long as the destination output port is available. In other words, an ATM cell is waiting at the input port. It will be passed through the switch using a cut through link, if the destination output port is available. On the other hand, it will be stored into the switch's shared buffers, if the destination output port is busy and the buffers are not full. Performance measures in terms of the end to end ATM cell delay, the switch cell delay, and the average number of cells queued in the shared buffers (defined as the required buffer size) are evaluated through simulation. In the simulation, it is assumed that the traffic load on each switch port is increased from 4 token rings (64 Mbps or 20% of port capacity) to 16 token rings (256 Mbps or 80% of port capacity). A simple model, based on the mean queue length of destination output ports, is used to analytically quantify the busy status of output ports. The simulation results point out that an ATM switch with cut through capability can significantly reduce the mean cell delay and the required buffer size, even when the probability of cells that can be cut through is very small.<>
Starting Page	578
Ending Page	584
File Size	692253
Page Count	7
File Format	PDF
ISBN	0780324927
DOI	10.1109/PCCC.1995.472435
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Asynchronous transfer mode Local area networks LAN interconnection Switches Buffer storage Delay Communication switching Telecommunication traffic Traffic control Token networks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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