NDLI: A performance evaluation methodology for computer systems

Content Provider	IEEE Xplore Digital Library
Author	Obaidat, M.S. Khalid, H.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. Eng., City Univ. of New York, NY, USA (Obaidat, M.S.; Khalid, H.)
Abstract	This paper presents a simulation methodology for evaluating the performance of CISC and RISC computer systems. Our method is called message flow technique (MFT). MFT is a modification of the instruction flow technique (IFT) we presented for RISC previously. The proposed methodology was applied to a single and two-level cache-based complex instruction set computer system using 80486 SX as a case study. Our trace driven simulations provide an estimate of the mean performance of the system for the considered general purpose computing environment with an accuracy of /spl plusmn/5% and a confidence level of 95%. The simulations indicate that with a single level on-chip cache of size 8 K bytes, the performance of the system is considerably limited by the service rime of bus interface unit (BIU). The average service time of bus interface unit, per instruction, was found approximately equal to 1.0135 microseconds for our synthetic workloads, collectively called, modified Gibson mix (MGM). With the introduction of a moderate-sized second level external cache to the system, the average performance improvement was found to be appreciable. The methodology presented here is an efficient and easy to use tool as compared to the previous methodologies, essentially limited to RISC architectures, that could help performance analysts in evaluating different computer systems.<>
Starting Page	713
Ending Page	719
File Size	627527
Page Count	7
File Format	PDF
ISBN	0780324927
DOI	10.1109/PCCC.1995.472415
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Reduced instruction set computing Analytical models Computer simulation Computer aided instruction Computer architecture Performance analysis Microprocessors Cities and towns Educational institutions
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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