NDLI: A new enhanced SPFD rewiring algorithm [logic IC layout]

Content Provider	IEEE Xplore Digital Library
Author	Cong, J. Lin, J.Y. Long, W.
Copyright Year	2002
Abstract	This paper presents an in-depth study of the theory and algorithms for the SPFD-based (set of pairs of functions to be distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70% higher than SPFD-based local rewiring algorithms (SPFD-LR) and 18% higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR). (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we study the impact of using different atomic SPFD pair assignment methods during the SPFD-based rewiring. We develop several heuristic atomic SPFD pair assignment methods for area or delay minimization and show that they lead to 10% more selected rewiring ability than the random (or arbitrary) assignment methods. When combining (1) and (2) together, we can achieve 38.1% higher general rewiring ability.
Sponsorship	IEEE Circuits & Syst. Soc. IEEE Comput. Soc. ACM/SIGDA
Starting Page	672
Ending Page	678
File Size	580988
Page Count	7
File Format	PDF
ISBN	0780376072
ISSN	10923152
DOI	10.1109/ICCAD.2002.1167604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire Algorithm design and analysis Field programmable gate arrays Minimization methods Network synthesis Logic Automatic test pattern generation Computer science Optimization methods Delay
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fast Boolean optimization by rewiring

Combinational logic synthesis for LUT based field programmable gate arrays

Improved alternative wiring scheme applying dominator relationship

Design rewiring using ATPG

A new enhanced SPFD rewiring algorithm

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Design rewiring for power minimization [logic design]

Delay optimization using SOP balancing

A new enhanced SPFD rewiring algorithm [logic IC layout]

Similar Documents

Fast Boolean optimization by rewiring

Combinational logic synthesis for LUT based field programmable gate arrays

Improved alternative wiring scheme applying dominator relationship

Design rewiring using ATPG

A new enhanced SPFD rewiring algorithm

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Design rewiring for power minimization [logic design]

Delay optimization using SOP balancing

A new enhanced SPFD rewiring algorithm [logic IC layout]