NDLI: Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors

Content Provider	IEEE Xplore Digital Library
Author	Bourgade, R. Rochange, C. Sainrat, P.
Copyright Year	2011
Description	Author affiliation: Institut de Recherche en Informatique de Toulouse, University of Toulouse, France (Bourgade, R.; Rochange, C.; Sainrat, P.)
Abstract	Multi-core architectures are now considered as possible candidates to implement future time-critical embedded systems. The challenge is to make the worst-case execution time (WCET) of each task predictable. In this paper, we investigate bus arbitration schemes with upper-bounded bus latencies. We focus on heterogeneous workloads in which tasks exhibit distinct requirements in terms of bandwidth. The proposed schemes perform a two-level arbitration: the cores are organized into groups and all the cores in the same group benefit from the same bandwidth. Different algorithms are considered to share the bus slots among the groups. Experimental results (WCET estimates) show an improved global WCET compared to usual round-robin schemes. This will enhance the schedulability of heterogeneous task sets.
Starting Page	1
Ending Page	4
File Size	591469
Page Count	4
File Format	PDF
ISBN	9781457700170
ISSN	19460759
e-ISBN	9781457700187
e-ISBN	9781457700163
DOI	10.1109/ETFA.2011.6059179
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-05
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Real time systems Bandwidth Resource management Multicore processing Equations Mathematical model
Content Type	Text
Resource Type	Article

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